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#1 June 14, 2010 10:09:49

Lorenzo M.
Registered: 2009-11-02
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[Kicad-developers] Another thing about module format


Another thing while you're working on the module format:

It would be useful the so-called 'playground', i.e. a bounding box
comprising the required reworking space. It could be even used during
DRC for detecting overlapped components.

The playground should be a simple bounding box, but manually defined
(since, for example, BGA requires a lot of tooling space for inspection
and replacement, while a simple MLCC only needs space for tweezers)

The IPC standards explain all in detail but it can be implemented in
a simple way.

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Lorenzo Marcantonio
Logos Srl

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#2 June 14, 2010 10:49:24

Werner A.
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[Kicad-developers] Another thing about module format


Lorenzo Marcantonio wrote:
> The playground should be a simple bounding box, but manually defined
> (since, for example, BGA requires a lot of tooling space for inspection
> and replacement, while a simple MLCC only needs space for tweezers)

What would constitute an invasion of the "playground" ? Another
component's playground ? Part of the package of another component ?
A pad of another component or a trace ?

Examples for each:
- test equipment attached to a component (clips, etc.)
- rework
- soldering accuracy, creepage/clearance distance

It's a very good point, though. I never liked the amount of
handwaving that goes into drawing component outlines because of
just this kind of issues.

- Werner

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#3 June 14, 2010 11:18:12

Lorenzo M.
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[Kicad-developers] Another thing about module format


On Mon, 14 Jun 2010, Werner Almesberger wrote:Lorenzo Marcantonio wrote:The playground should be a simple bounding box, but manually defined
(since, for example, BGA requires a lot of tooling space for inspection
and replacement, while a simple MLCC only needs space for tweezers)What would constitute an invasion of the "playground" ? Another
component's playground ? Part of the package of another component ?
A pad of another component or a trace ?Only another playground... its the "bounding tile" of the component,
needed for testing/replacing it. The standards for example gives about
1mm for BGA since you need space for inspection and the reworking nozzle
(there is a special optical probe for looking *under* the chip, to avoid
x-raying the board).

Oh, BTW the official term is 'courtyard' :D

IPC-7351A define it as:

"The smallest rectangular area that provides a minimum electrical and
mechanical clearance (courtyard excess) around the compined component
body and land pattern boundaries."

To put thing simply you first compute the 'electrical' courtyard
(bounding box of the pads *with* their isolation clearance), then you
compute the mechanical one (the body plus some 'courtyard excess', which
is tabulated for component type), then pick the rectangle containing
*both* of these... in other word it's not something you can compute
automatically without access to the full IPC standard (the free land
pattern calculator gives it, anyway). So I would expect a button like
the 'component origin' to select the two corners of the courtyard
(ideally it would be on yet another layer).Examples for each:
- test equipment attached to a component (clips, etc.)These are mostly *over* but for a turret test point it would be useful.- reworkMostly this- soldering accuracy, creepage/clearance distanceNot exactly... pad clearance are for these things. The playground is
mostly a mechanical, not electrical thing. OTOH the pad clearance
contribute to it, so, yes, in a way.It's a very good point, though. I never liked the amount of
handwaving that goes into drawing component outlines because of
just this kind of issues.You you read the standard there is no handwaving... you pick the maximum
material condition (i.e. the biggest that a component can get out of the
factory) and this would be the silkpad (some people instead use the
nominal size for silkpad, but without the courtyard it could be risky).
The courtyard simply encloses all the manufacturing constraint for
a given fabrication level (I always use nominal, BTW, since it gives 99%
yield anyway, in our experience).

The trouble is during component placement... it's easy to put a 0603under a big TQFP (which is of course physically impossible... butsocketed PGA are an exception) :D. A courtyard based DRC would signalthis (and the autoplacer could use it too, altough I've *never* seen it
doing a decent work).

The IPC standards suggest a clearance of 0,05mm (the standard grid pitch)
about playgrounds but even a simple intersection check would be useful
(OTOH we already have the pad-pad collision routines, so it's almost
free).

--
Lorenzo Marcantonio
Logos Srl

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#4 June 14, 2010 11:22:31

Werner A.
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[Kicad-developers] Another thing about module format


I wrote:
> What would constitute an invasion of the "playground" ?

BTW, here are some thoughts on clearance (for electrical reasons,
but much of this should also apply to mechanical clearance):http://lists.openmoko.org/pipermail/gta02-core/2009-September/000583.htmlOnly the list at the beginning is relevant to this discussion.
The rest is about chip resistors and such.

In the posting, "clearance" refers to a global clearance.
"Component" refers to the component's package.

- Werner

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#5 June 14, 2010 12:15:59

Werner A.
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[Kicad-developers] Another thing about module format


Lorenzo Marcantonio wrote:
> Only another playground... its the "bounding tile" of the component,

Hmm, but if you use it mainly for rework, adjacent components could
share the courtyard, no ? After all, you'll inspect or (de)solder
them one by one, not simultaneously.

Also, what do you do with components with a very non-rectangular
shape, e.g., SOT-23 and friends ?

> in other word it's not something you can compute
> automatically without access to the full IPC standard

Sigh. I wish the standard was a bit more free ...

> You you read the standard there is no handwaving...

Sorry, I meant what we're currently doing in KiCad for mechanical
clearance (and to some extent for electrical clearance as well,
i.e., where there's metal with no pad underneath.)

The problem with handwaving is that it's contagious. Make all your
keep out zones pessimistic (i.e., large) and people will get into
the habit of violating them because they know they can get away
with it. Make them optimistic, and each will introduce their own
"safety factor".

Same thing with disallowing overlapping keep out areas that can
overlap in practice. (That's why I brought up that point.)

Hmm, wouldn't it be nice for making hobbyist-friendly layouts if
we had the placement tolerance as a parameter, like we have the
clearance right now ? Of course, changing it would also have to
grow pads and such ...

- Werner

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#6 June 14, 2010 14:03:50

Lorenzo M.
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[Kicad-developers] Another thing about module format


On Mon, 14 Jun 2010, Werner Almesberger wrote:Hmm, but if you use it mainly for rework, adjacent components could
share the courtyard, no ? After all, you'll inspect or (de)solder
them one by one, not simultaneously.It would be difficult to say 'how much' they can overlap... I think they
calculated them 'in-average', keeping in account this... for example for
the typical 0603-or-bigger chip package the nominal excess is 0,25mm
which is by itself insufficient for tweezers (the WTA-1 need 0,5mm to
fit in). But keeping *two* resistors side by side (0,25+0,05
intercourtyard clearance+0,25) allow access (in real world what happen
usually is: you want to desolder one resistor and the near four ones get
loose too :().Also, what do you do with components with a very non-rectangular
shape, e.g., SOT-23 and friends ?As a good layout rule of thumb you don't "nest" components, most of the
time, it's considered bad form:D also the standard is already
sufficiently complex, only using a bounding box!Sigh. I wish the standard was a bit more free ...I agree... for professional use the price is trivial (about 60 EUR
IIRC), but for hobby use it a barrier to entry... (if you look around
you can find 'leaked' copies, anyway :P)

Also of 96 pages only 20 contains the needed data for calculations, the
other mostly contains explanation of how components are made (like:
a SOIC has a pitch of 1,27 ...) and manufacturing details (compliance
testing and tray/tape/reel formats).The problem with handwaving is that it's contagious. Make all your
keep out zones pessimistic (i.e., large) and people will get into
the habit of violating them because they know they can get away
with it. Make them optimistic, and each will introduce their own
"safety factor".The main issue is that there's a lot of process dependant parameters
here... I can do a 6mil tech board without problem but if possible
I would make it in 8mil tech because yield is better (so it's cheaper).
Also some fabs have milling tolerances of 0,2mm instead of 0,1mm, so
what do you use for clearance to the edge of the board? (it only get
sicker from there, like 0,2mm on outer edges but 0,1mm on pockets, or
different tolerances depending on drill size!). You also have to keep
track of pick-and-place tolerances, how much boards will be 'shaken'
from site bombing and reflow and how much rework you can tolerate. The
'minimum/median/maximum' levels in the standard are a way to unificate
all these issues (and with the 'least' protrusion, i.e. high density,
you *must* do test runs to determine if process yield is acceptable).Same thing with disallowing overlapping keep out areas that can
overlap in practice. (That's why I brought up that point.)In my experience usually you can use that space to put some via and/or
difficult-to-route trace:DHmm, wouldn't it be nice for making hobbyist-friendly layouts if
we had the placement tolerance as a parameter, like we have the
clearance right now ? Of course, changing it would also have to
grow pads and such ...Placement tolerances *are* a parameter in the IPC formulas (there is
a whole theory of minimum material conditions and so on, like doing the
RMS of the tolerances...). The defaults in the LP Calculator (it's free,
but you need to register) are 0,05mm (i.e. one point on the standard
grid) but you can change all of them in the preferences...

Also, a good operator with a suitable magnification tool can place
components even *better* than the site bomber (the trick is that during
reflow surface tension in solder realign the component - usually).

The ideal thing would be someone porting the IPC formulas for generating
.emp files (side note: the LP Calculator is free but they make you pay
big bucks for the cad export options!)

--
Lorenzo Marcantonio
Logos Srl


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