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#1 Nov. 16, 2005 07:39:16

v.
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[avr-gcc-list] how to infer lsl instruction...


Hello all,i'm usingavr-gcc
(GCC) 3.4.3 compiler and Atmega 16 as a MCU. for crc calculation i'm using inline assembly
code.for example.. __asm__
__volatile__         (               "lsl r11"    "\n\t"     "rol r12"    "\n\t"     "rol r13"    "\n\t"     "rol r15"   ); but compiler doesn't generate lsl
instruction...it generates something like this..     1514: bb
0c        add r11,
r11    1516: cc 1c      
 adc r12, r12    1518: dd
1c        adc r13,
r13    151a: ff 1c      
 adc r15, r15  so what should do to if i want compiler to generate
lsl instruction. thank you,  regards,varsha--***********************Confidentiality Notice***************************The information contained in this electronic message and any attachmentsto this message are intended for the exclusive use of the addressee(s)and may contain confidential or privileged information. If you are notthe intended recipient, please notify the sender at Divinet or immediately and destroy all copies of thismessage and any attachments.************************************************************************_______________________________________________
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#2 Nov. 16, 2005 08:36:41

Royce P.
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[avr-gcc-list] how to infer lsl instruction...


HiOn Wed, 16 Nov 2005 13:00:03 +0530, varsha <>wrote:Hello all,
i'm using avr-gcc (GCC) 3.4.3 compiler and Atmega 16 as a MCU.

for crc calculation i'm using inline assembly code.
for example..

__asm__ __volatile__
(
"lsl r11" "\n\t"
"rol r12" "\n\t"
"rol r13" "\n\t"
"rol r15"
);

but compiler doesn't generate lsl instruction...
it generates something like this..

1514: bb 0c add r11, r11
1516: cc 1c adc r12, r12
1518: dd 1c adc r13, r13
151a: ff 1c adc r15, r15


so what should do to if i want compiler to generate lsl instruction.If the bytes & execution time is the same, why should make any difference,as long as it acheives the same result. Left shift is the same asmultiplying by 2, which is the same as adding a value to itself. Hence theresulting code.--Royce.thank you,


regards,
varsha
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#3 Nov. 16, 2005 10:59:13

Lars N.
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[avr-gcc-list] how to infer lsl instruction...


* varsha <> :__asm__ __volatile__("lsl r11" "\n\t""rol r12" "\n\t""rol r13" "\n\t""rol r15");

but compiler doesn't generate lsl instruction...
it generates something like this..

1514: bb 0c add r11, r11
1516: cc 1c adc r12, r12
1518: dd 1c adc r13, r13
151a: ff 1c adc r15, r15Look at the Atmel AVR instruction set datasheet, and you will see, that
"lsl r" and "rol r" have the same opcodes as "add r,r" and "adc r,r".

The compiler outputs exactly the inline assembly you entered, but you
are looking at the disassembler output. And the disassembler has no way
to know, which mnemonic was used in the source code.


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#4 Nov. 16, 2005 11:47:06

Eric P.
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[avr-gcc-list] how to infer lsl instruction...


If you take a look to the "8-bits AVR Instruction Set" document, you can seethat "LSL Rd" is implemented as "ADD Rd,Rd", and "ROL Rd" as "ADC Rd,RD".There are no specific instructions LSL or ROL.
Welcome to the RISC world (REDUCED Instruction Set Computers) !

Best regards,
Eric.----- Original Message -----From: "Royce Pereira" <>To: "varsha" <>; <avr-gcc-l***@*ongnu.org>
Sent: Wednesday, November 16, 2005 9:16 AM
Subject: Re: how to infer lsl instruction...HiOn Wed, 16 Nov 2005 13:00:03 +0530, varsha <>wrote:Hello all,
i'm using avr-gcc (GCC) 3.4.3 compiler and Atmega 16 as a MCU.

for crc calculation i'm using inline assembly code.
for example..

__asm__ __volatile__
(
"lsl r11" "\n\t"
"rol r12" "\n\t"
"rol r13" "\n\t"
"rol r15"
);

but compiler doesn't generate lsl instruction...
it generates something like this..

1514: bb 0c add r11, r11
1516: cc 1c adc r12, r12
1518: dd 1c adc r13, r13
151a: ff 1c adc r15, r15


so what should do to if i want compiler to generate lsl instruction.If the bytes & execution time is the same, why should make any difference,as long as it acheives the same result. Left shift is the same asmultiplying by 2, which is the same as adding a value to itself. Hence theresulting code.--Royce.thank you,


regards,
varsha
***********************Confidentiality Notice***************************

The information contained in this electronic message and any attachments
to this message are intended for the exclusive use of the addressee(s)
and may contain confidential or privileged information. If you are not
the intended recipient, please notify the sender at Divinet or
immediately and destroy all copies of this
message and any attachments.

************************************************************************--
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#5 Nov. 16, 2005 12:01:01

David B.
Registered: 2009-11-02
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[avr-gcc-list] how to infer lsl instruction...


> Hi
> On Wed, 16 Nov 2005 13:00:03 +0530, varsha <>
> wrote:
>
> > Hello all,
> > i'm using avr-gcc (GCC) 3.4.3 compiler and Atmega 16 as a MCU.
> >
> > for crc calculation i'm using inline assembly code.
> > for example..
> >
> > __asm__ __volatile__
> > (
> > "lsl r11" "\n\t"
> > "rol r12" "\n\t"
> > "rol r13" "\n\t"
> > "rol r15"
> > );
> >
> > but compiler doesn't generate lsl instruction...
> > it generates something like this..
> >
> > 1514: bb 0c add r11, r11
> > 1516: cc 1c adc r12, r12
> > 1518: dd 1c adc r13, r13
> > 151a: ff 1c adc r15, r15
> >
> >
> > so what should do to if i want compiler to generate lsl instruction.
>
> If the bytes & execution time is the same, why should make any difference,
> as long as it acheives the same result. Left shift is the same as
> multiplying by 2, which is the same as adding a value to itself. Hence the
> resulting code.
>
> --Royce.
>

If you've got the code space, crc checks are far more efficiently done using
a table rather than bit for bit. For an 8-bit crc, this takes 256 bytes and
gives you a one-line C function for the check code. For 16-bit crc, it
takes 512 bytes and two lines of C. For fast and compact assembly, you can
also use a 4-bit lookup table.

mvh.,

David




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#6 Nov. 16, 2005 17:56:18

Terry K.
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[avr-gcc-list] how to infer lsl instruction...


Lars Noschinski wrote:Look at the Atmel AVR instruction set datasheet, and you will see, that
"lsl r" and "rol r" have the same opcodes as "add r,r" and "adc r,r".The document this thread is referring to is most likelyhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf.

For those who haven't encountered all of these yet, the complete list is:

SBR -> ORI
CBR -> ANDI
TST -> AND
CLR -> EOR
LSL -> ADD
ROL -> ADC
all branch instructions -> BRBS, BRBC

For example, in the above document, in the particular entry for CLR,
with "16-bit Opcode" it says "see EOR Rd,Rd" (which one has certainly
seen if they've looked at disassembly). (It would have been nice if all
these equivalencies were more than just hinted at in the table summary.)

Even BRGE and BRLT, which formally depend on both the N and V bits, are
done with BRBS and BRBC via the S bit. On the other hand, this is why
there is no "BRGT" (branch if greater than zero, signed) nor "BRLE"
(branch if less than or equal, signed).

-Terry Karlson




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